Silicon possibilities: Aura Direct Hardware

The short answer

How many process steps?

Not seven. “7 nm” names a process generation. Modern node names are performance, density and design-rule labels, not a single measured transistor dimension.

Intel says an advanced wafer undergoes thousands of processing steps. Its manufacturing guide records more than 50 masks across all chip layers. ASML describes hundreds of manufacturing operations and repeated lithography cycles.

The exact A12, Snapdragon, Dimensity and Kirin mask counts and recipes remain commercial secrets. Public evidence reaches the foundry’s published process family.

Intel: thousands of wafer steps ↗
Intel: more than 50 masks (PDF) ↗
ASML: how chips are made ↗

Three different counts

Node

7 nm, 5 nm, 3 nm, 2 nm

A foundry generation. Smaller labels usually signal higher density or efficiency, but labels are not directly comparable between foundries.

Masks

Patterned layers

Reticles transfer different device and interconnect patterns. Multiple patterning and EUV choices change the total.

Operations

Thousands of fab steps

Deposition, coating, exposure, etch, implantation, cleaning, polishing, inspection and metrology recur across the wafer flow.

Who is at that level?

The mobile SoC field.

Nominal node is one column among CPU architecture, NPU, GPU, modem, memory, packaging, software, power and volume.

The buttons reveal the A12-era cohort and the current leading cohort separately or together. “Current” means publicly launched by 9 August 2026; Australian availability varies by device.

Selected A12-era and current mobile system-on-chip reference points
Designer / chip	Launch	Published process	Position	What the comparison really says
Apple A12 Bionic	2018	7 nm; 6.9B transistors	Flagship phone	Apple’s reference point: custom CPU/GPU plus an eight-core Neural Engine. Closed Apple IP.
Huawei HiSilicon Kirin 980	2018	TSMC 7 nm; 6.9B	Flagship phone	The closest nominal A12-era peer: same published node and transistor count, different architecture and ecosystem.
Qualcomm Snapdragon 855	2018 announcement / 2019 devices	7 nm	Flagship phone	A commercial platform supplied to device makers; its register-transfer-level design and modem IP remain closed.
Samsung Exynos 9825	2019	7 nm EUV	Flagship phone	Samsung combines silicon design and foundry capability; device use has largely been internal.
MediaTek Dimensity 1000	2019	7 nm	Flagship 5G phone	MediaTek became a full flagship competitor after the A12’s launch year.
Apple A19 / A19 Pro	2025	Third-generation 3 nm	Flagship phone	Leading vertically integrated reference; still not a licensable Aura design.
Qualcomm Snapdragon 8 Elite Gen 5	2025	3 nm	Flagship Android	Custom Oryon CPU and a broad modem/XR ecosystem make Qualcomm a practical platform partner before custom silicon.
MediaTek Dimensity 9500	2025	TSMC N3P	Flagship Android	A leading 3 nm-class alternative with CPU, GPU, NPU, imaging and modem integration.
Samsung Exynos 2600	2026	Samsung 2 nm GAA	Flagship phone	A different foundry label and transistor architecture; “2 nm” alone does not prove it beats every 3 nm product.
Xiaomi XRING O1	2025	3 nm; 19B transistors	Flagship phone / tablet	Shows another device company entering clean-sheet mobile SoC design, backed by major capital and supply-chain support.
Huawei HiSilicon Kirin 9030	2025, reported	Not published in an official source identified in this review	Reported flagship phone	This register treats it as third-party reporting; node and detailed capability remain unverified in Huawei sources.
Google Tensor G5	2025	Not published on Google’s product pages	Flagship phone	Google optimises for its own AI and camera experience; that workload-specific thinking is more useful than copying a benchmark.

Adjacent leaders span NVIDIA in high-power AI and robotics modules, AMD and Intel in CPUs, FPGAs and edge compute, plus NXP, Renesas, STMicroelectronics, Texas Instruments and Microchip in industrial, automotive, safety and long-life embedded systems. They are highly capable, but not direct flagship-phone equivalents.

Architecture choice

Arm is a licence. RISC‑V is an open instruction set.

Neither one is a finished Aura chip. A usable SoC brings together verified cores, memory, interconnect, security, debug, analogue blocks, interfaces, package, software, test and manufacturing.

Working experiment Current modules

Present compute modules

Arm routes such as Snapdragon, NXP and NVIDIA sit beside AMD and other x86 systems, FPGAs and specialised accelerators. Aura’s software and surrounding board remain open to ownership, alteration and replacement.

How Arm licensing works ↗

Research Arm design route

Arm building blocks

Cortex, Ethos, Mali, CoreLink and security IP are one available design vocabulary. Apple-style custom CPU cores use a deeper architecture licence and larger engineering effort.

Arm Flexible Access ↗

Research Open path

RISC‑V foundations

The instruction-set architecture is open and royalty-free. Specific core implementations, peripherals and physical IP carry open, restricted or commercial licences, each with its own terms.

RISC‑V International ↗
OpenROAD register-transfer level to chip-layout flow ↗

Choose your own silicon adventure

Experiment branches in every direction.

Every card is an entry point. Several sit together, old ideas reopen and entirely new branches appear as people acquire information and their needs evolve.

Use what exists

Existing-silicon exploration

Aura models and sensor flows run on available hardware. Public measurements support comparison; private experiments stay with their builders.

Clean sheet

Complete-SoC design

Mature and advanced nodes, licensed and open cores, chiplets and clean-sheet designs remain in view. Scale is one reason for this branch; sovereignty, resilience, curiosity and discovery are others.

Reconfigurable

FPGA rewiring

Sensor fusion, image processing, inference, new processor ideas and architectures nobody has named yet all find room here, beside software comparisons and curiosity-led experiments.

Fabrication

Small-batch ASIC fabrication

MPW shuttles and other accessible foundry routes carry one block, many blocks or a strange new architecture into silicon. A batch serves learning, teaching, physical tests, art, products or purposes its builders discover along the way.

Physical system

Owned boards and interfaces

Carrier boards, power, sensors, radios, local storage and controls take whatever mix of open, salvaged, commercial and home-built modules fits the question.

Inside a chosen tape-out

Fabrication has physical dependencies.

A chosen design becomes working silicon through linked engineering states. AI explores and optimises across the chain while people choose the architecture, evidence threshold and consequences carried by each experiment.

Versioned design intent for this tape-out.
Architecture partition across CPU, NPU, DSP, FPGA, MCU and fixed logic.
Foundry, process, package, PDK and design-partner choices.
Recorded licences for hardware and software intellectual property.
Executable reference models and a corresponding software stack.
Integrated digital and analogue or mixed-signal design.
Simulation, formal verification, emulation and coverage evidence.
FPGA prototypes for uncertain logic.
Synthesis, design-for-test insertion and equivalence evidence.

Floorplan, placement, clock-tree construction and routing.
Timing, power, integrity, IR-drop and thermal convergence.
DRC, LVS and foundry sign-off evidence.
Signed-off GDSII or OASIS for tape-out.
Computationally corrected mask data derived from the design.
Wafer fabrication, process characterisation and yield observations.
Wafer probe, packaging, final test, burn-in and reliability evidence.
Key provisioning, board and firmware validation, plus certification evidence associated with the chosen use.
One device, ten or thousands, followed by yield learning and another design choice.

Scale reality

Advanced nodes cost a lot. Cost is one input among many.

A 2023 SIA/BCG industry model, converted at the Reserve Bank of Australia’s 7 August 2026 reference rate, gives total design costs of about AUD 41 million for 65 nm, AUD 73 million for 28 nm, AUD 424 million for 7 nm, AUD 771 million for 5 nm and more than AUD 1.42 billion for 3 nm.

Those are broad converted industry estimates, not a quote, mask-set price, inflation adjustment or forecast for Aura. Conversion formula: AUD = reported foreign-currency amount ÷ 0.7029, using the RBA reference rate for 7 August 2026. Mature-node MPW prototypes are often vastly cheaper. Builders weigh commercial efficiency beside learning, sovereignty and discovery, then select the route that fits their own values.

SIA/BCG design-cost model, page 11 (PDF) ↗ · RBA conversion reference ↗

Decision information

What trade-offs does this batch carry?

break-even units = total custom-silicon NRE ÷ per-unit saving

For commercial-scale questions, this equation sits beside yield, packaging, respins and support. It gives commercial context while every idea keeps its own purpose and value.

Open fabrication starts small. Open PDKs, Tiny Tapeout and MPW shuttles support learning through real silicon. A first batch teaches, challenges an architecture, builds local capability, creates art, begins a product or opens another question.